The present invention relates to a method of forming an isolation layer of a semiconductor memory device and, more particularly, to a method of forming an isolation layer from a high-density plasma (HDP) oxide layer.
In a semiconductor circuit, it is necessary to isolate unit elements, such as transistors, diodes and resistors, which are formed over a semiconductor substrate. This isolation process is an initial process for the semiconductor fabrication process and determines the size of an active region and process margin of a subsequent process.
As a method of forming this isolation layer, a local oxidation of silicon (LOCOS) method has been used frequently. However, because of this LOCOS isolation method, oxygen penetrates into the sides of a pad oxide layer under a nitride layer used as a mask upon selective oxidization of a semiconductor substrate, so a bird's beak is generated at the corners of a field oxide layer. This bird's beak causes the field oxide layer to expand into the active region to a depth as long as the length of the bird's beak. Thus, the channel length is shortened and the threshold voltage is increased accordingly. Consequently, the electrical properties of, for example, a transistor is degraded.
Meanwhile, a shallow trench isolation (STI) process has emerged as an isolation process which can solve problems, such as unstable factors in the process, including degradation of the field oxide layer due to a reduction in the design rule of a semiconductor device, and a reduction of the active region due to the bird's beak.
FIG. 1 is a sectional view illustrating a conventional method of forming an isolation layer of a semiconductor memory device.
Referring to FIG. 1, a tunnel insulating layer 11 and a polysilicon layer 12 for a floating gate are formed over a semiconductor substrate 10. The polysilicon layer 12, the tunnel insulating layer 11, and the semiconductor substrate 10 are selectively etched to thereby expose an isolation region of the semiconductor substrate 10. Trenches 13 are formed by etching the exposed semiconductor substrate 10. The trenches 13 are gap-filled with an insulating layer, forming isolation layers (or isolation structures) 14.
Here, before the isolation layers 14 are formed, a series of processes, including a sidewall sacrificial oxidization process of the trenches 13 (for the purpose of removing etch defects on the semiconductor device due to a dry etch), a sidewall re-oxidization process of the trenches 13, etc., are performed. Description of the series of the processes is omitted for simplicity.
To increase the integration level of semiconductor memory devices, the device size has been reduced to 60 nm or less. Thus, for a semiconductor memory using the self-aligned shallow trench isolation (SA-STI) process, it becomes difficult to secure a gap-fill margin employing a HDP oxide layer. Accordingly, a spin on dielectric (SOD) oxide layer is used in order to secure sufficient gap-fill margin. However, if an isolation layer is formed using the SOD layer, the process costs are increased and the reliability of elements is degraded due to the physical properties of the SOD layer.